Current and future generation DRAM and SDRAM applications utilize very high I/O speeds. As a result, the clock speeds are also very high. The high clock speeds may make aligning phases and setting duty cycles of clocks challenging, as timing windows and margin for error are both very narrow. The narrow margins may result in reduced reliability when correcting phase differences or detecting a duty cycle error, which may cause data to be unreliably communicated between a host and a memory.